The present invention relates to an integrated circuit having two or more cooperating circuit sections.
Integrated circuits of this type are, for example, representative of the integrated circuits which experts refer to as xe2x80x9ccore based systemsxe2x80x9d or xe2x80x9csystems on siliconxe2x80x9d or xe2x80x9ccircuits with embedded macrosxe2x80x9d. In integrated circuits of this type, a first circuit section (core or embedded macro) is embedded in a second circuit section.
An integrated circuit constructed in this way has a first circuit section, a second circuit section, and connecting lines between the first circuit section and the second circuit section.
In this case, the first circuit section is often an existing function block which is xe2x80x9cmerelyxe2x80x9d embedded in a new environment (the second circuit section). The use of existing and tested components facilitates the configuration of the relevant integrated circuits. Integrated circuits constructed in this way are comparatively fast and simple to construct.
However, difficulties occasionally arise when testing such integrated circuits, to be precise particularly when the first circuit section and the second circuit section are intended to be tested separately independently of one another.
It is difficult to test the first circuit section separately because in very many cases its input and/or output terminals are, at least in part, accessible only via the surrounding second circuit section. Therefore, it is difficult to test the second circuit section separately because its function is (concomitantly) influenced by the first circuit section embedded in it (by data or signals output from the first circuit section to the second circuit section).
It is accordingly an object of the invention to provide in an integrated circuit having a scan register chain which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the circuit sections can be tested separately and independently of one another with a low outlay under all circumstances.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit containing at least two cooperating circuit sections including a first circuit section and a second circuit section, the circuit sections having input terminals and output terminals. An interface containing at least one scan register chain connects the first circuit section to the second circuit section. Input/output terminals are connected to the interface. The scan register chain receives data selectively from the input/output terminals and the output terminals of one of the circuit sections. The data is output selectively from the scan register chain to the input terminals of one of the circuit sections and to the input/output terminals. The scan register chain receives the data output from the output terminals of one of the circuit sections and then outputs the data via the scan register chain to the input/output terminals. The data fed to and stored in the scan register chain from outside the integrated circuit is output to the input terminals of one of the circuit sections.
Accordingly, it is provided that the circuit sections are connected to one another through the interface containing the scan register chain. The scan register chain is configured to the effect that data can be input into the scan register chain optionally via the output terminals of one of the circuit sections or via the input and/or output terminals of the integrated circuit. The data can be output from the scan register chain optionally to the input terminals of one of the circuit sections or to the input and/or output terminals of the integrated circuit.
The provision of one or more scan register chains in the interface between the circuit sections enables direct and complete access to the input and/or output terminals of the respective circuit sections. Data loaded into the scan register chain(s) from outside the integrated circuit can be applied to the input terminals of the respective circuit sections, and data output from the output terminals of the respective circuit sections can be written to the scan register chain(s) and output via the latter from the integrated circuit.
Such access to the input and/or output terminals of the respective circuit sections enables the cooperating circuit sections to be completely decoupled (isolated from one another). Therefore, there is no longer a need or a necessity for the signals or data that are to be input into a circuit section or output therefrom to be conducted via the other circuit section.
By virtue of the fact that the at least one scan register chain is configured to the effect that data can be input into the scan register chain optionally via the output terminals of one of the circuit sections or via the input and/or output terminals of the integrated circuit, and/or that data can be output from the scan register chain optionally to the input terminals of one of the circuit sections or to the input and/or output terminals of the integrated circuit, the number of scan register chains which is necessary for access to the input and/or output terminals of the respective circuit sections can be kept to a minimum. This is because the at least one scan register chain has a dual function. It can have data that are output from the output terminals of a circuit section written to it and output the data from the integrated circuit, or it can have data written to it from outside the integrated circuit and output these data to the input terminals of a circuit section.
Consequently, an integrated circuit has been found whose circuit sections can be tested separately independently of one another with a low outlay under all circumstances.
In accordance with an added feature of the invention, the interface contains a multiplicity of interface units, one of the interface units is provided for each connection between the first circuit section and the second circuit section.
In accordance with an additional feature of the invention, the interface units each contain a register, the register from each of the interface units are connected up to form the at least one scan register chain.
In accordance with another feature of the invention, the interface units each contain a multiplexer connected upstream of the input terminals of the circuit sections. The multiplexer selectively switches through a signal fed in during normal operation and a further signal to a respective input terminal of the circuit sections.
In accordance with a further feature of the invention, the further signal is output by the register of a respective one of the interface units and the further signal is a signal input through the input/output terminal.
In accordance with a concomitant feature of the invention, the at least one scan register chain is configured to subject a sequence of the data that are input in parallel to a signature analysis.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit having a scan register chain, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.